1. Field of the Invention
The present invention relates to a pass gate circuit and a method of controlling same. More particularly, the invention relates to a pass gate circuit and a related control method that provide improved meta-stability during signal transfer.
2. Description of the Related Art
So-called pass gate circuits are commonly used in the circuits forming semiconductor memory device. In this context, many pass gate circuits are used to facilitate switching operations. For example, a pass gate circuit may be used to implement a latched data output circuit in a semiconductor memory device. Pass gate circuits are turned ON/OFF in response to a control signal. When turned ON, a pass gate circuit will receive and output an input signal. When turned OFF, the output of the received input signal by the pass gate circuit is disabled.
Figure (FIG.) 1 is a circuit diagram of a conventional pass gate circuit 10. Referring to FIG. 1, pass gate circuit 10 includes a transfer controller 11 and a latch 12. Transfer controller 11 includes a pass gate PG implemented with a Complementary Metal Oxide Semiconductor (CMOS) element configured with at least one inverter. Latch 12 includes at least one inverter to latch a received signal until it is output. An initial input signal “A” is the input signal to be transferred through pass gate circuit 10. An external control signal “B” is applied as a control signal to the control electrode of pass gate PG. Thus, control signal B controls the transfer of input signal A through pass gate circuit 10. Furthermore, signal C is the output signal of pass gate circuit 10.
Unfortunately, conventional pass gate circuit 10 can operate in an unstable mode when input signal A and control signal B simultaneously transition from one logic level to another. During unstable operation, the output signal from pass gate circuit 10 becomes unstable such that its amplitude decreases to thereby cause a meta-stability problem.
FIG. 2 is a waveform diagram illustrating an unstable signal transfer by pass gate circuit 10. Referring to FIG. 2, input signal A and control signal B simultaneously transition from a logically high level (hereafter “high”) to a logically low level (hereafter “low”). When control signal B transitions to low, the pass gate PG is turned OFF and current cannot be supplied to the input terminal of pass gate circuit 10, and the output of the pass gate PG becomes unstable.
Output signal C from pass gate circuit 10 varies in relation to input signal A. Pass gate circuit 10 operates normally when input signal A transitions outside the period when control signal B transitions. However, when input signal A and control signal B transition simultaneously, output signal C follows input signal A after a predetermined delay time. As a result, and as illustrated in FIG. 2, a completely different output signal waveform is obtained over that which is intended under normal operation of pass gate circuit 10.